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Digital Logic | verilog

FPGA Counter and LED Display System

FPGA-based counter system featuring LED and 7-segment display control using Verilog and digital logic design.

Description

This project documents the design and implementation of a frequency divider with a 4-bit bidirectional counter and decoder on the Intel DE0-CV FPGA board. The project integrates three key components:

  • A 25-bit frequency divider (LPM counter) to slow the 50MHz clock to ~1.5Hz.
  • A 4-bit up/down counter with enable/clear controls.
  • A hex-to-7-segment decoder and 4-bit GPIO LED pattern generator.

The system demonstrates counters, decoders, and FPGA I/O interfacing (onboard LEDs, 7-segment display, and breadboard LEDs). All functionalities were verified through simulation and hardware testing.

Pictures

FPGA counter project image three
FPGA counter and LED display setup.
FPGA counter project image one
Hardware view during testing and demonstration.
FPGA counter project image two
Completed FPGA project output view.

Video Demo